1. Field of the Invention
The present invention relates to a novel logical comb filter and, more particularly, to a logical comb filter used by video apparatus to separate the luminance signal (Y) from the chrominance signal (C) therein.
2. Description of the Prior Art
The so-called logical comb filter has been known and used to separate vertically the luminance signal (Y) from the chrominance signal (C) in video apparatus. What this filter does is to have logic circuits carry out comparisons of three line signals of the past (1 horizontal scanning period earlier), present and future (1 horizontal scanning period later) so as to minimize signal irregularities (dot disturbance, discoloring, etc.) resulting from the use of the signals with low vertical correlation.
FIG. 6 shows a typical logical comb filter "a" of the NTSC standard. In the figure, reference character "b" designates an input terminal through which a composite signal (hereinafter called (Y+C).sub.I) is input. The input signal (Y+C).sub.I is sent via a 1H delay line "c" to a subtracter "d". The input terminal is also sent to a band pass filter "e"whose center frequency is f.sub.sc (color subcarrier frequency).
The signal in the vicinity of f.sub.sc, when extracted by the band pass filter "e", is placed onto a 1H delay line "g" via a NOT circuit "f" (the output signal from the NOT circuit "f" is called A.sub.0 ; The symbol "-" means an inversion of phase effected on the output signal from the band pass filter "e".). The signal on the 1H delay line "g" is then sent to a NOT circuit "h" that generates a signal delayed by 1H relative to the signal A.sub.0 (called signal A.sub.1).
In addition, a 1H delay line "i" and a NOT circuit "j" downstream thereof provide a signal (called signal A.sub.2) delayed by 1H relative to the signal A.sub.1.
The three line signals A.sub.0, A.sub.1 and A.sub.2, obtained with the 1H time spacing therebetween, are processed by logic operation units "k" and l (these units comprise MAX and MIN circuits, the MAX circuits extracting the signals whose levels are the highest, the MIN circuits extracting the signals whose levels are the lowest).
Specifically, in the logic operation unit "k", the signals A.sub.0 and A.sub.1 are input to a MIN circuit "m" and the signals A.sub.1 and A.sub.2 to a MIN circuit "n". The outputs from the MIN circuits "m" and "n" are sent to a MAX circuit "o" whose output is in turn sent to an adder "p".
In the logic operation unit l, the signals A.sub.0 and A.sub.1 are input to a MAX circuit "q" and the signals A.sub.1 and A.sub.2 to a MAX circuit "r". The outputs from the MAX circuits "q" and "r" are sent to a MIN circuit "s" whose output in turn is sent to the adder "p".
The output from the adder "p" is output as a C (chrominance) signal (called signal C.sub.0) via a multiplier "t" having a coefficient of 1/2. The adder output is also sent to the subtracter "d" wherein the signal C.sub.0 is subtracted from the 1H delayed signal of the input signal (Y+C).sub.I to provide a luminance signal (called signal Y.sub.0).
In the above-described logical comb filter "a", the three line signals A.sub.0, A.sub.1 and A.sub.2 are processed according to the following two algorithms:
(1) If the level of the signal A.sub.1 is between those of the signals A.sub.0 and A.sub.2, the signal A.sub.1 is adopted as the signal C.sub.0.
It is assumed that V.sub.0, V.sub.1 and V.sub.2 designate the levels of the signals A.sub.0, A.sub.1 and A.sub.2, respectively. If V.sub.0 &lt;V.sub.1 &lt;V.sub.2 or if V.sub.0 &gt;V.sub.1 &gt;V.sub.2, then the intermediate level signal A.sub.1 is output as the signal C.sub.0.
For example, the case where V.sub.0 &lt;V.sub.1 &lt;V.sub.2, as conceptually illustrated in FIG. 7 (A), is considered. In FIG. 7, the vertical axis stands for delay times .tau. and the vertical axis for signal levels V. The levels V.sub.0, V.sub.1 and V.sub.2 are indicated by hollow circles (.largecircle.).
In the logic operation unit "k" of the case above, the MAX circuit "o" selects the signal A.sub.1, which has the higher signal level and is obtained by the MIN circuit "n", in preference to the signal A.sub.0 acquired by the MIN circuit "m"; the selected signal A.sub.1 is sent to the adder "p". In the logic operation unit l, the MIN circuit "s" selects the signal A.sub.1, which has the lower signal level and is obtained by the MAX circuit "q", in preference to the signal A.sub.2 acquired by the MAX circuit "r"; the selected signal A.sub.1 is sent to the adder "p". It follows that the mean output level obtained by the adder "p" and the multiplier "t" is V.sub.1, which is exactly the same as in the case where the signal A.sub.1 is adopted. The other algorithm is:
(2) If the level of the signal A.sub.1 is not between those of the signals A.sub.0 and A.sub.2, the mean level between the signal A.sub.1 and the either signal whose signal level is the closer to that of the former is adopted as the output level of the signal C.sub.0.
That is, if V.sub.1 &gt;V.sub.2 or V.sub.1 &lt;V.sub.0 where V.sub.0 &lt;V.sub.2 or, conversely, if V.sub.1 &lt;V.sub.2 or V.sub.1 &gt;V.sub.0 where V.sub.0 &gt;V.sub.2, a comparison is made between .vertline.V.sub.1 -V.sub.0 .vertline. and .vertline.V.sub.1 -V.sub.2 .vertline.. What is adopted here is the mean level between V.sub.1 and the signal level (V.sub.0 or V.sub.2) which is the lower of the two.
For example, in the logic operation unit "k" and where V.sub.0 &lt;V.sub.2 &lt;V.sub.1, as depicted in FIG. 7 (B), the MAX circuit "o" selects the signal A.sub.2, which is obtained by the MIN circuit "n" and has the higher signal level, in preference to the signal A.sub.0 acquired by the MIN circuit "m"; the selected signal A.sub.2 is sent to the adder "p". In the logic operation unit l, the MAX circuits "q" and "r" both yield the signal A.sub.1 ; the signal A.sub.1 is then sent from the MIN circuit "s" to the adder "p". What is adopted here is a signal with a level (V.sub.1 +V.sub.2)/2, the signal being acquired by the adder "p" and subtracter "t". That is, the mean output between the level V.sub.1 and the level V.sub.2 which is the closer of the remaining two to the former is used as the signal C.sub. 0.
In the above-described logical comb filter "a", the two kinds of signal processing are carried out as described centering on the signal A.sub.1 : (1) where vertical correlation between the three line signals is high, or (2) where the vertical correlation between the three line signals is low.
One disadvantage of the above logical comb filter "a" is that the logic operation units "k" and l comprise a large number of component devices. Another disadvantage of the prior art logical comb filter is that it is difficult to modify the circuit configuration thereof.
That is, many comparators used in the MIN and MAX circuits constituting the logic operation units "k" and l boost the number of gates, which pushes up the cost.
The reason that the circuit configuration is difficult to modify is that the decision on signal selection is not separated from the actual selection of signals in the logic operation units "k" and l (in fact, the two kinds of processing are mixed therein).
In the logical comb filter "a", any modification of or addition to the algorithms used requires major revisions in the configuration of the logic operation units. In that case, it is difficult to foresee how the eventual circuit configuration will turn out to be, because the existing arrangements hardly provide adequate guidelines to the modification or addition required.
For example, with the algorithms (1) and (2) described above, the Y/C separation is neatly carried out at a vertical edge involving transition from the portion with the chrominance signal to the portion without it. By contrast, where a vertical stripe pattern "v" of the Y signal having the F.sub.sc component appears on a monitor screen "u", irregularities occur at edges "w" and "w'".
FIG. 8 (B) conceptually describes the above situation. With respect to the lower edge "w'" of the stripe pattern "v", three lines, i.e., n-th, (n+1)th and (n+2)th, are extracted and partially illustrated.
FIG. 8B-1 shows how the luminance of the edge "w'" appears on the screen. In the figure, "H" stands for a bright portion and "L" for a dark portion.
FIG. 8B-2 depicts the situation in effect after signal passage through the band pass filter "e". Only those signals with large changes in luminance (i.e., at high frequencies) pass the filter on the n-th and (n+1)th scanning lines. The signal passage is blocked on the (n+2)th scanning line (as indicated by symbol ".phi.").
FIG. 8B-3 illustrates the situation in effect after the phase is reversed. With the signal of the (n+1)th line taken as the center, the phase of that signal is opposite to that of the signal of the line on the n-5h line.
FIG. 8B-4 shows the situation in effect after processing is carried out by the logical comb filter "a" according to the above-described algorithm (2). In FIG. 8B-4, "H/2" and "L/2" mean that the luminance levels are about half that of the H portion and half that of the L portion, respectively.
That is, in FIG. 8B-3, the signal of the (n+1)th line is judged to be closer to the (n+2) line signal than to the n-th line signal whose phase is reversed by the algorithm (2).
For example, regarding the portion "x" enclosed by broken lines in FIG. 8B-2, the signal level V.sub.0 of the n-th line and the signal level V.sub.1 of the (n+1)th line are about V.sub.H after passage through the band pass filter "e", as depicted in the upper graphic representation of FIG. 8C. The signal level V.sub.2 of the (n+2)th line is close to zero.
The output of the band pass filter "e" is reversed in phase every time the output is delayed by 1H by the NOT circuit "f" downstream of the filter or by the NOT circuits "h" and "j" downstream of the 1H delay lines "g" and "i". Thus the signal level of the n-th line is -V.sub.0 (the signal level V.sub.2 remains at approximately zero after phase reverse wherein V.sub.2 .apprxeq.0).
In this manner, the signal level V.sub.1 is judged to be the closest to the signal level V.sub.2 according to the algorithm (2). The mean value V.sub.12 (=(V.sub.1 +V.sub.2)/2 .congruent.V.sub.1 /2) is adopted as the C.sub.0 signal.
Where the algorithm (2) is to be followed, the mean value is obtained between V.sub.1 and the signal level close thereto. This means that the emphasis is on the processing of the chrominance signal regarding the f.sub.sc component of the signal. Thus the f.sub.sc component of the Y signal is adopted as the C signal and processed as such.
This disadvantage is avoided by the following measure: Where the levels of the three line signals are in a specific relation with one another, these levels may be judged to be the f.sub.sc component of the Y signal and may be suppressed from getting output as the signal C.sub.0. For example, the average may be obtained between the two farthest signal levels.
In the example above, as shown in the lower graphic representation of FIG. 8C, the signal levels V.sub.1 and -V.sub.0 are averaged, the latter being the farthest from the former, i.e., V.sub.12 =(-V.sub.0 +V.sub.1)/2 .congruent.0. In that case, the mean level is not regarded as the chrominance signal. Instead, the level V.sub.H is extracted unmodified as the level of the signal Y.sub.0.
What has been considered above has focused on the bright portion "x". The same applies to the transition from the dark portion next to the bright portion "x" to the next adjacent bright portion (the only difference is in signal levels).
Where the level relationship between the three line signals is judged to be the f.sub.sc component of the Y signal as described, a new algorithm (3) is adopted. The algorithm (3) is stipulated as follows:
If there is a need to regard the level of the signal A.sub.1 as the Y signal even though the signal level does not fall between the levels of the signals A.sub.0 and A.sub.2, the mean level between V.sub.1 and the signal level farthest therefrom is adopted as the output level of the signal C.sub.0.
The trouble is that when it comes to practicing the algorithm (3) above, it has been conventionally difficult even to envisage the kind of improvement that would be needed for the construction of the logic operation units "k" and l.